View CY7C1051DV33-12ZSXI_8323795.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1051dv33 8-mbit (512 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00063 rev. *h revised september 22, 2011 8-mbit (512k x 16) static ram features temperature ranges ? ?40 c to 85 c high speed ? t aa = 10 ns low active power ? i cc = 110 ma at f = 100 mhz low cmos standby power ? i sb2 = 20 ma 2.0-v data retention automatic power-down when deselected transistor-transistor logic (ttl)-compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 48-ball fine ball grid array (fbga) and 44-pin thin small outline package (tsop) ii packages functional description the cy7c1051dv33 is a high performance cmos static ram organized as 512 k words by 16-bits. to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 ?i/o 7 ), is written into the location specified on the address pins (a 0 ?a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 ?i/o 15 ) is written into the location specified on the address pins (a 0 ?a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 ?i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the ?truth table? on page 9 for a complete description of read and write modes. the input/output pins (i/o 0 ?i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or a write operation (ce low, and we low) is in progress. the cy7c1051dv33 is available in a 44-pin tsop ii package with center power and ground (revolutionary) pinout and a 48-ball fbga package. 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 512 k 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 18 a 9 a 10 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce we ble bhe logic block diagram
cy7c1051dv33 document #: 001-00063 rev. *h page 2 of 15 contents pin configurations ........................................................... 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics over the operating range ............................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 over the operating range ............................................... 5 data retention waveform ................................................ 5 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 read cycle no. 1 ........................................................ 7 read cycle no. 2 (oe controlled) .............................. 7 write cycle no. 1 (ce controlled) ............................... 8 write cycle no. 2 (ble or bhe controlled) ................ 8 write cycle no. 3 (we controlled, oe low) ............. 9 truth table ........................................................................ 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15
cy7c1051dv33 document #: 001-00063 rev. *h page 3 of 15 pin configurations figure 1. pin diagram - 48-ball fbga (top view) [1] figure 2. pin diagram - 44-pin tsop ii (top view) [1] \ we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 a 18 selection guide description ?10 ?12 unit maximum access time 10 12 ns maximum operating current 110 100 ma maximum cmos standby current 20 20 ma note 1. nc pins are not connected on the die.
cy7c1051dv33 document #: 001-00063 rev. *h page 4 of 15 maximum ratings exceeding the maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65 c to +150 c ambient temperature with power applied............................................ ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5 v to +4.6 v dc voltage applied to outputs in high-z state [2] ...................................?0.3 v to v cc + 0.3 v dc input voltage [2] ...............................?0.3 v to v cc + 0.3 v current into outputs (low)..........................................20 ma static discharge voltage............. ...............................>2001 v (per mil-std-883, method 3015) latch-up current ...................................................... >200 ma operating range range ambient temperature v cc speed industrial ?40 c to +85 c3.3 v 0.3 v 10 ns industrial ?40 c to +85 c3.3 v 0.3 v 12 ns dc electrical characteristics over the operating range parameter description test conditions ?10 ?12 unit min max min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 ? 0.4 v v ih [2] input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il [2] input low voltage ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc ? 110 ? 100 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max ?40?35ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ?20?20ma note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 2.0 v for pulse durations of less than 20 ns. capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 12 pf c out i/o capacitance 12 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions fbga package tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 28.31 51.43 c/w jc thermal resistance (junction to case) 11.4 15.8 c/w
cy7c1051dv33 document #: 001-00063 rev. *h page 5 of 15 data retention characteristics over the operating range data retention waveform ac test loads and waveforms ac characteristics (except high-z) are test ed using the load conditions shown in figure 3 (a). high-z characteristics are tested for all speeds using the test load shown in figure 3 (c). figure 3. ac test loads and waveforms 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 50 1.5 v (a) 3.3 v output 5 pf ( c) r 317 r2 351 high-z characteristics (b) parameter description conditions [3] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?20ma t cdr [4] chip deselect to data retention time 0?ns t r [4] operation recovery time t rc ?ns 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 3. no inputs may exceed v cc + 0.3 v 4. full device operation requires linear v cc ramp from v dr to v cc (min) > 50 s or stable at v cc (min) > 50 s.
cy7c1051dv33 document #: 001-00063 rev. *h page 6 of 15 ac switching characteristics over the operating range [5] parameter description ?10 ?12 unit min max min max read cycle t power [6] v cc (typical) to the first access 100 ? 100 ? s t rc read cycle time 10 ? 12 ? ns t aa address to data valid ? 10 ? 12 ns t oha data hold from address change 2.5 ? 2.5 ? ns t ace ce low to data valid ? 10 ? 12 ns t doe oe low to data valid ? 5 ? 6 ns t lzoe oe low to low-z 0 ? 0 ? ns t hzoe oe high to high-z [7, 8] ?5?6ns t lzce ce low to low-z [8] 3?3?ns t hzce ce high to high-z [7, 8] ?5?6ns t pu ce low to power up 0 ? 0 ? ns t pd ce high to power down ? 10 ? 12 ns t dbe byte enable to data valid ? 5 ? 6 ns t lzbe byte enable to low-z 0 ? 0 ? ns t hzbe byte disable to high-z ? 5 ? 6 ns write cycle [9, 10] t wc write cycle time 10 ? 12 ? ns t sce ce low to write end 7 ? 8 ? ns t aw address setup to write end 7 ? 8 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7 ? 8 ? ns t sd data setup to write end 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z [8] 3?3?ns t hzwe we low to high-z [7, 8] ?5 6ns t bw byte enable to end of write 7 ? 8 ? ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v. 6. t power gives the minimum amount of time that the power supply must be at typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , t hzbe and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ?ac test loads and waveforms? on page 5.transition is measured when the outputs enter a high impedance state. 8. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe , and t hzwe is less than t lzwe for any device. 9. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and hold timing must refer to the leading edge of the sig nal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1051dv33 document #: 001-00063 rev. *h page 7 of 15 switching waveforms read cycle no. 1 figure 4. read cycle no. 1 [11, 12] read cycle no. 2 (oe controlled) figure 5. read cycle no. 2 [12, 13] previous data valid data out valid t rc t aa t oha address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data i/o v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb notes 11. device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 12. we is high for read cycle. 13. address valid before or coincident with ce transition low.
cy7c1051dv33 document #: 001-00063 rev. *h page 8 of 15 write cycle no. 1 (ce controlled) figure 6. write cycle no. 1 [14, 15] write cycle no. 2 (ble or bhe controlled) figure 7. write cycle no. 2 switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t data in valid t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce data in valid notes 14. data i/o is high-impedance if oe , or bhe , ble , or both = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state.
cy7c1051dv33 document #: 001-00063 rev. *h page 9 of 15 write cycle no. 3 (we controlled, oe low) figure 8. write cycle no. 3 switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe data in valid truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high-z high-z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high-z read lower bits only active (i cc ) l l h h l high-z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high-z write lower bits only active (i cc ) l x l h l high-z data in write upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc )
cy7c1051dv33 document #: 001-00063 rev. *h page 10 of 15 ordering code definitions ordering information cypress offers other versions of this ty pe of product in many different configurat ions and features. the following table contai ns only the list of parts that are currently available. for a comp lete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales r epresentative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's represent atives and distributors. to find the office closest t o you, visit us at http://www.cypress.com /go/datasheet/offices. speed (ns) ordering code package diagram package type operating range 10 cy7c1051dv33-10baxi 51-85193 48-ba ll fbga (pb-free) industrial cy7c1051dv33-10zsxi 51-85087 44-pin tsop ii (pb-free) 12 cy7c1051dv33-12baxi 51-85193 48-ba ll fbga (pb-free) industrial CY7C1051DV33-12ZSXI 51-85087 44-pin tsop ii (pb-free) contact your local cypress sales repres entative for availability of these parts. temperature range: x = i or e i = industrial package type: xxx = bax or zsx bax = 48-ball fbga (pb-free) zsx = 44-pin tsop ii(pb-free) speed: xx = 10 ns or 12 ns or 15 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 1 = data width 16-bits 05 = 8-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 v33 - xx xxx 7 05 1 d x
cy7c1051dv33 document #: 001-00063 rev. *h page 11 of 15 package diagrams figure 9. 48-ball fbga (6 x 8 x 1.2 mm), 51-85193 51-85193 *c
cy7c1051dv33 document #: 001-00063 rev. *h page 12 of 15 figure 10. 44-pin thin small outline package type ii, 51-85087 package diagrams (continued) 51-85087 *d
cy7c1051dv33 document #: 001-00063 rev. *h page 13 of 15 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory soj small outline j-lead tsop thin small outline package vfbga very fine-pitch ball grid array symbol unit of measure ns nanosecond vvolt a microampere ma milliampere mv millivolt mw milliwatt mhz megahertz pf picofarad c degree celsius wwatt
cy7c1051dv33 document #: 001-00063 rev. *h page 14 of 15 document history page document title: cy7c1051dv33, 8-mbit (512 k 16) static ram document number: 001-00063 revision ecn orig. of change submission date description of change ** 342195 pci see ecn new datasheet *a 380574 syt see ecn redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 110, 90 and 80 ma to 110, 100 and 95 ma for 8, 10 and 12 ns speed bins respectively i cc (ind?l): changed from 110, 90 and 80 ma to 120, 110 and 105 ma for 8, 10 and 12 ns speed bins respectively changed the capacitance values from 8 pf to 10 pf on page # 3 *b 485796 nxr see ecn changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed -8 and -12 speed bins from product offering, removed commercial operating range option, modified maximum ratings for dc input voltage from -0.5 v to -0.3 v and v cc + 0.5 v to v cc + 0.3 v changed the description of i ix from input load current to input leakage current. changed t hzbe from 5 ns to 6 ns updated footnote #7 on high-z parameter measurement added footnote #11 updated the ordering information table and replaced package name column with package diagram. *c 866000 nxr see ecn changed ball e3 from v ss to nc in fbga pin configuration *d 1513285 vkn/aesa see ecn converted from preliminary to final changed t hzbe from 6 ns to 5 ns for 10 ns speed bin added 12 ns speed bin changed t oha spec from 3 ns to 2.5 ns updated ordering information table *e 2911009 vkn 04/12 /10 replaced 48-ball (7 x 8.5 x 1.2 mm) fbga with 48-ball (6 x 8 x 1.2mm) fbga, updated package diagrams, updated ordering information. *f 3086522 pras 11/15/2010 included auto-e information (preliminary) in ordering information . *g 3112625 aju 12/16/2010 added ordering code definitions . *h 3369149 tava 09/12/2011 removed all references to automotive information.
document #: 001-00063 rev. *h re vised september 22, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1051dv33 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C1051DV33-12ZSXI

	To Download CY7C1051DV33-12ZSXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .